Predictor-Dependent Amplification of Branch Mispredictions in Out-of-Order Superscalar Processors: A RISC-V gem5 O3 Study

Branch prediction errors can reduce superscalar throughput by more than the error frequency alone suggests because a single misprediction can trigger redirect, squash, refetch, refill, and window recovery, which collectively disrupt sustained instruction-level parallelism. This paper presents a quantitative framework that relates prediction accuracy to realized parallelism loss in out-of-order superscalar processors. The framework separates prediction-error frequency, effective recovery cost, and unrealized issue capacity using prediction accuracy (Acc), misprediction rate (MR), effective branch penalty in cycles per misprediction (BP), parallelism loss ratio (PLR), the ratio-based branch sensitivity factor BSF=PLR/MR, and the slope-based branch sensitivity factor S-BSF=∂PLR/∂MR. BSF measures how strongly a particular processor configuration and workload convert prediction errors into lost issue capacity, whereas S-BSF provides a more stable sensitivity estimate when MR approaches zero. The framework is evaluated using timing-detailed gem5 O3 simulations on RV64GC workloads. The evaluation includes controlled branch microbenchmarks and six GAPBS graph workloads, allowing the proposed metrics to be examined under both mechanism-isolating and complex workload conditions. Two complementary controlled sweeps are used. At a fixed processor structure, predictor family and predictor level are varied to determine whether changing the predictor strengthens or weakens the relationship between MR and IPC/PLR. At a fixed predictor configuration, issue width and an effective front-end-depth proxy are varied to measure how the microarchitecture amplifies the performance cost of the remaining prediction errors. Thus, issue width is treated as an amplification variable for branch-prediction failures rather than as an independent performance topic. At the fixed structural point, Tournament and BiMode predictors show strong monotonic MR–PLR relationships on the high-branch benchmark, with Spearman coefficients of 1.00 and 0.98, whereas the Local predictor exhibits nearly unchanged MR but materially different IPC and PLR across levels. This demonstrates that the mapping from MR to throughput depends on predictor family and configuration rather than being invariant. In the controlled structural sweep, increasing issue width from 4 to 8 raises PLR by 37.6% and BSF by 55.0% on the high-branch benchmark, even though MR remains in the same order of magnitude. On GAPBS workloads, the lowest-MR configuration is not always the highest-IPC configuration, confirming that effective branch penalty and parallelism loss must be considered together with prediction frequency. These numerical findings are conditional on the evaluated single-thread gem5 DerivO3CPU model, RV64GC binaries, predictor implementations, memory hierarchy, and workload set. They characterize predictor–microarchitecture interactions in this controlled simulation environment and should not be interpreted as universal constants for all processors or applications.