Modular Real-Time FPGA Implementation of SDFT Pre-Processing and Hardware-Optimized MLP Inference for Visible Light Positioning Receivers

This paper presents an FPGA feasibility study of two digital processing blocks for a future real-time Visible Light Positioning (VLP) receiver: a Sliding Discrete Fourier Transform (SDFT) stage for carrier-magnitude extraction and a hardware-optimized Multi-Layer Perceptron (MLP) inference engine for coordinate estimation. The localization model is trained and evaluated offline with experimental data from the four-photodiode VLP system reported in the reference work, whereas the SDFT and MLP FPGA blocks are validated separately on a physical Visible Light Communication (VLC) hardware platform. Therefore, the reported 1–2 mm spatial accuracy belongs to the offline reference dataset and model, whereas the FPGA results quantify module latency, numerical fidelity, implementation resources, and tool-estimated power, not physical end-to-end coordinate accuracy. The design was implemented on a AMD Xilinx Zynq-7000 (xa7z020clg484-1Q) SoC FPGA device and operated at 100 MHz. The SDFT block requires 61,655 clock cycles, corresponding to 616.55 μs, while the MLP variants require between 607 and 6612 clock cycles, corresponding to 6.07 μs and 66.12 μs, respectively. All MLP implementations reproduce the offline software reference with HW/SW MSE values on the order of 10−6. The resulting blocks and the reported first HLS integration estimates establish an implementation path while identifying the acquisition, synchronization, and multi-tone validation work still required for a complete receiver.