Hardware reconfigurable secure data acquisition system of a shared ADC in heterogenous multi-channel inputs with automatic sampling frequency configurations

Abstract Multi-channel Data Acquisition (DAQ) Systems can use a single multiplexed analog to digital converter (ADC) to reduce system cost. But this ADC must be configured to proper sampling rate for each channel. In this paper, a novel algorithm is proposed to automatically generate ADC configuration, and improve the ADC’s utilization and utility, reduce the number of redundant bits, and reduce cost. This proposed algorithm is mathematically formulated, and numerical examples are given. The research methodology involves using FPGA board with analog to digital and digital to analog conversion card, and synthetic wave form is generated and captured for verification. In this phase, a single channel is investigated, as the investigation of multi-channel DAQ requires the integration and scheduling of the ADC with an external analog multiplexer. In prior work, a custom computer board is designed to implement the HTMS algorithm for 32 analog channels. To effectively demonstrate the previously proposed HTMS superiority against other approaches, new performance metrics were defined, namely the ADC’s utilization, utility and efficiency using two different heuristic analog input sets. These metrics show that the HTMS-based DAQ outperforms relevant systems as it reaches 100% of ADC’s utilization and utility, while other systems have 75% utilization, and 6.25% utility. By devising a unified figure of merit for multiple DAQ systems, it is shown that the proposed system is higher by 218% compared to the baseline multi-channel DAQ system. Furthermore, Advanced Encryption Standard (AES) has been extensively investigated for cryptographic applications. A given pipelined 54-cycle AES-256-bit key core is considered for enhancement. With a single cycle design approach, the given core is successfully implemented in FPGA device using only 14-cycles / round, and generating a maximum encryption throughput of 12.8 Gb/s, with an FPGA utilization of only 9% Cyclone V SX SoC 5CSXFC6D6F31C6N, with speed up factor of 7 times is reported, compared to recent results, operating at a maximum clock frequency of 100 MHz. The proposed system will have a broader impact, particularly in medical diagnosis and prognosis, where multiple sensors of heterogenous types are used simultaneously, and the collected data must be secured to protect subjects’ privacy.