PROPEL: A Memory-Driven, Adaptive Vector-Flow-Field Router with Process-Aware Waveguide Generation for Large-Scale Photonic Integrated Circuits

Photonic integrated circuits (PICs) are rapidly increasing in scale and routing complexity, driven by photonic computing, optical switching, programmable interferometer meshes, wavelength-routed optical networks-on-chip, and chip-to-chip optical interconnects. Manual waveguide planning becomes increasingly impractical as designs approach hundreds to thousands of photonic components, because routing must satisfy geometric, optical, electrical, and manufacturing constraints. This paper presents Photonic Routing Optimization and Placement Engine (PROPEL) , a memory-driven, native-accelerated adaptive vector-flow-field routing framework with process-aware waveguide generation for large-scale PIC physical design. PROPEL builds a routing kernel based on a bounded vector-flow-field algorithm and design-rule checking (DRC) validation. The same kernel supports passive optical routing, active optical–electrical routing, and topology-driven net assignment. C++ accelerates computationally intensive field and routing calculations, while Python performs detailed DRC replay, legality checking, route commitment, and GDSFactory-based geometry generation. Compared with state-of-the-art routing solutions, PROPEL is faster on 17 of 18 shared passive-routing cases, with a median speedup of 2.6 × and a geometric-mean speedup of 2.5 ×, while maintaining zero final design-rule violations. PROPEL also supports active optical–electrical routing, topology-driven net assignment, length, delay, and optical-path-length matching, process-map-aware waveguide generation, route-memory reuse, selective rip-up/reroute, and Graphic Data System (GDSII)-level legality replay. These capabilities address heterogeneous PIC layouts where optical, electrical, process, topology, matching, and manufacturability constraints must be handled together. In incremental-layout experiments, PROPEL restores more than 95% of previously verified routes after small local component movements and reroutes only the affected subset, reducing modified-design routing from tens or hundreds of seconds to a few seconds while maintaining zero final design-rule violations.