TEL-RAM: A Specialized Memory Architecture for Energy-Efficient Acceleration via Thermo-Electric Sensing

This Version(1.1) is Repaired For Version 1.0 This paper proposes TEL-RAM (Thermo-Electric Loop RAM), a memory architecture that de-couples storage, readout, and maintenance functions. Using a storage coil, passive electromagnetic sensing, and thermal-based replenishment control, TEL-RAM achieves ultra-low read energy (˜0.1–1pJ), minimal write energy (<0.01 pJ), and extremely low standby power (˜0.017 pW/bit). The cell requires multiple switches and a comparator, resulting in a larger area (˜1.0–2.0 μm2 at 28nm) compared to DRAM, positioning it as a specialized accelerator memory rather than a general-purpose DRAM replacement. Due to its cell area (˜1.0–2.0 μm2/bit at 28nm), TEL-RAM is not suited for large-scale mainmemory or for enabling “space-for-time” trade-offs at capacity. Instead, it functions as a specialized,low-density accelerator memory for read-intensive, batch-write-dominant, and energy-constrained workloads. A complete energy model, latency analysis, thermal time constant verification, SNR estimation, and area breakdown are provided. The architecture is compared against SRAM, DRAM,MRAM, and ReRAM, with clear positioning for AI inference, edge computing, and 2.5D heterogeneous integration.