Simulations of p‐Channel GaN‐Based Metal‐Oxide‐Semiconductor Heterostructure Field‐Effect Transistors for Normally Off Operation

An improved p‐channel metal oxide semiconductor (MOS) heterostructure field effect transistor (HFET) is proposed for a normally off operation with its counterpart n‐channel MOS‐HEMT in a CMOS GaN HFET power logic technology. The performance of the p‐channel MOS‐HFET is simulated using Silvaco device TCAD based on a transport model calibrated against experimental data. The improved MOS‐HFET design uses a combination of 2 nm AlGaN and 1 nm AlN cap layers to raise the electrostatic potential and to deplete a 2D hole gas channel below the gate contact, thereby achieving a negative threshold voltage. An increase in the drain current of more than 300% is achieved when the device is laterally scaled down to a 250 nm gate length. The proposed device exhibits a threshold voltage of approximately −4.5 V and a substantially higher on‐current of 22 mA/mm, enhancing its potential for future complementary MOS (CMOS) integrated circuits.