A Power-Efficient 256-bit Overlap-Free Karatsuba Multiplier Architecture for ECC on FPGA Platforms

Elliptic Curve Cryptography (ECC) has emerged as a preferred security mechanism for resource-constrained Internet-of-Things (IoT) platforms due to its high security-to-key-size ratio. In hardware implementations of ECC over binary extension fields GF(2m), finite-field polynomial multiplication constitutes the most power-intensive operation. This work presents a power-efficient 256-bit overlap-free Karatsuba multiplier architecture implemented over GF(2m) and evaluated on the Xilinx Virtex-7 (xc7vx690tffg1761-2) FPGA platform. Binary extension fields are specifically chosen for their carry-free XOR-based arithmetic, which reduces logic depth and switching activity – advantages particularly suited to low-power FPGA implementations.Two distinct architectural strategies are investigated: a fully instantiated hierarchical design and an iterative, resource-shared design. While the instantiated architecture achieves minimal latency through parallel computation, it incurs excessive switching activity and power dissipation. In contrast, the proposed iterative architecture employs a Finite State Machine (FSM) to enable controlled hardware reuse, thereby significantly reducing switching activity.Post-synthesis analysis using Xilinx Vivado 2014.2 demonstrates that the iterative architecture achieves a reduction of approximately 89.5% in estimated dynamic power (from 590.37 W to 62.00 W) and 88.9% in total on-chip power (from 599.658 W to 66.325 W), at the cost of a 90.1% increase in LUT utilization (from 16,429 to 31,223). An analytical power model based on Karatsuba complexity is presented, confirming that dynamic power scales with exponent β ≈ 1.58 (instantiated) and β ≈ 1.54 (iterative), both closely consistent with the theoretical Karatsuba complexity (log2 3 ≈ 1.585). The relevance of binary polynomial multiplication in emerging Post-Quantum Cryptography (PQC) schemes highlights the broader applicability of the proposed architecture.

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Journal
IETE Journal of Research
Published
2026-07-30
DOI
https://doi.org/10.1080/03772063.2026.2699925
Primary Topic
Low-power high-performance VLSI design
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article
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article

A Power-Efficient 256-bit Overlap-Free Karatsuba Multiplier Architecture for ECC on FPGA Platforms

V. R. Venkatasubramani, S. Rajaram, R. RajaRaja, A. Babu Karuppiah
IETE Journal of Research
Low-power high-performance VLSI design
article

A Power-Efficient 256-bit Overlap-Free Karatsuba Multiplier Architecture for ECC on FPGA Platforms

V. R. Venkatasubramani, S. Rajaram, R. RajaRaja, A. Babu Karuppiah
article en

Abstract

Elliptic Curve Cryptography (ECC) has emerged as a preferred security mechanism for resource-constrained Internet-of-Things (IoT) platforms due to its high security-to-key-size ratio. In hardware implementations of ECC over binary extension fields GF(2m), finite-field polynomial multiplication constitutes the most power-intensive operation. This work presents a power-efficient 256-bit overlap-free Karatsuba multiplier architecture implemented over GF(2m) and evaluated on the Xilinx Virtex-7 (xc7vx690tffg1761-2) FPGA platform. Binary extension fields are specifically chosen for their carry-free XOR-based arithmetic, which reduces logic depth and switching activity – advantages particularly suited to low-power FPGA implementations.Two distinct architectural strategies are investigated: a fully instantiated hierarchical design and an iterative, resource-shared design. While the instantiated architecture achieves minimal latency through parallel computation, it incurs excessive switching activity and power dissipation. In contrast, the proposed iterative architecture employs a Finite State Machine (FSM) to enable controlled hardware reuse, thereby significantly reducing switching activity.Post-synthesis analysis using Xilinx Vivado 2014.2 demonstrates that the iterative architecture achieves a reduction of approximately 89.5% in estimated dynamic power (from 590.37 W to 62.00 W) and 88.9% in total on-chip power (from 599.658 W to 66.325 W), at the cost of a 90.1% increase in LUT utilization (from 16,429 to 31,223). An analytical power model based on Karatsuba complexity is presented, confirming that dynamic power scales with exponent β ≈ 1.58 (instantiated) and β ≈ 1.54 (iterative), both closely consistent with the theoretical Karatsuba complexity (log2 3 ≈ 1.585). The relevance of binary polynomial multiplication in emerging Post-Quantum Cryptography (PQC) schemes highlights the broader applicability of the proposed architecture.

IETE Journal of Research
PSG INSTITUTE OF TECHNOLOGY AND APPLIED RESEARCH (IN), Sri Eshwar College of Engineering
Affordable and clean energy
Openalex Percentile: Top 16%
Low-power high-performance VLSI design
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