Disturb‐Resilient and Wake‐up‐Free 2T‐MFMFET Array for Storage and Computing Applications

ABSTRACT HfO 2 ‐based ferroelectric (FE) memories are promising candidates for embedded nonvolatile memory (eNVM). However, conventional FE memory structures still face critical trade‐offs among area and voltage scalability, endurance, and retention. To address these limitations, the 2T‐MFMFET has been proposed as a hybrid architecture that combines the robust retention and endurance of FeRAM with the superior area and voltage scalability of MFMFET. Although its device‐level potential has been demonstrated, experimental validation at the array level has remained largely unexplored. Here, we present the array‐level study of the 2T‐MFMFET fabricated using a standard FeRAM‐compatible process flow. The array exhibits wake‐up‐free operation and disturb‐resilient potential under the tested array‐bias schemes, together with a large memory window of 1 V, 3‐bit multi‐level‐cell (MLC) storage capability, and extremely tight device‐to‐device distributions. Array‐level retention and endurance are verified up to 10 4 s and 10 4 cycles, respectively, while extended single‐device cycling further supports the potential to exceed FeRAM benchmarks. Furthermore, a new hybrid in‐memory computing (IMC) scheme is proposed that exploits the long‐retention 2T‐MFMFET state for storage and the short‐retention internal MFMFET state for computing. Our proof‐of‐concept demonstration suggests a possible route toward low operating overhead, high data fidelity, and low standby power in future IMC implementations.