Evaluation of Single-Event Upsets in SRAM in 22 nm Fully Depleted Silicon in an Insulator Integrated Circuit Process

The fully depleted silicon on insulator (FDSOI) integrated circuit process has a buried oxygen layer in its structure, which provides many advantages to the FDSOI integrated circuit process, such as isolating the substrate from the conductive channel, reducing leakage current, and lowering the supply voltage. With the vigorous development of space artificial intelligence infrastructure in China and the United States, it is becoming increasingly important to study the single-event upset (SEU) of Static Random-Access Memory (SRAM) cells caused by particle radiation. In this paper, SRAM with different peripheral circuits is designed by domestically produced 22 nm FDSOI CMOS integrated circuit technology. Simulations are used to study the mechanism of single-event effects for SRAM, and single-particle radiation experiments of Kr are used to characterize SEU for SRAM. The results showed that the SRAM without Error Detection and Correction (EDAC) technology had 6486 cell upsets, with incidences of 2-cell upsets occurring 15 times, and no multi-cell flips occurred. For the SRAM using EDAC technology, there was no single-cell upset, 430 incidences of two-cell upsets and one incidence of multi-cell upsets. This provides strong support for fully utilizing EDAC technology to enhance the irradiation-hardening of digital integrated circuits. For metal oxide semiconductor field-effect transistors, the source and drain structures are completely symmetrical, and when in use, they are only connected at different potentials.