Heterogeneous Dual-Rail Computation via Chinese Remaindering on Binary Hardware

The radix economy of base-3 surpasses binary by approximately 5.68% due to its proximity to Euler's number, the theoretical optimum for digit-based number systems. Despite this mathematical advantage, physical ternary logic circuits remain absent from commercial hardware because of fundamental semiconductor constraints: three distinct voltage levels halve the available noise margin and induce static leakage current in the middle state. Prior efforts to circumvent this limitation have relied on either inefficient bit-pairing—allocating two binary bits per ternary digit, which wastes 25% of the state space—or complex multi-word simulation that fails to exploit the native carry chains of standard Arithmetic Logic Units (ALUs). This work presents a fundamentally different approach: the application of the Chinese Remainder Theorem (CRT) to pack two independent numbers, one binary and one ternary, into a single integer word. By leveraging the Diophantine approximation 3ᵐ ≈ 2ⁿ, derived from the continued fraction expansion of log₂(3), the CRT modulus M = 2ⁿ·3ᵐ is shown to fit within exactly 2n bits for the optimal convergent pairs, including the foundational (5 → 8) and the high-efficiency (41 → 65) packings. A formal proof demonstrates that a standard binary adder, operating on this packed integer, simultaneously computes addition modulo 2ⁿ and modulo 3ᵐ without any modification to the carry propagation logic. The only necessary hardware alterations are peripheral: a threshold comparator for ternary overflow, and a Barrett reduction unit for residue extraction. Quantitatively, this scheme delivers a 1.67-fold increase in arithmetic throughput for linear workloads compared to a single n-bit ALU, at a silicon area overhead of less than 12% and a 16.7% reduction in dynamic energy per operation. The extraction tax, which incurs a three-cycle latency per read of the ternary residue, is shown to be amortized to near-zero for loops exceeding eight iterations. Compression synergies, including topological pruning, delta encoding, and control-plane sparsity, are examined alongside system-level implications such as ISA extensions, memory management, security properties, and deployment strategies for mobile versus server environments. The fundamental limitations—the impossibility of preserving total order in a ring isomorphism, the physical bound of the carry chain, and the extraction lower bound—are rigorously characterized, establishing the CRT scheme as a specialized accelerator mode rather than a universal replacement for binary logic.