A 128-Stage High-Precision Analog Accumulator Utilized for TDI-CMOS Image Sensors

A 128-stage high-precision analog accumulator is proposed for TDI-CMOS image sensors, incorporating a decoupling capacitor multiplication technique and a noise sampling compensation circuit. The proposed decoupling capacitor multiplication technique enlarges the effective decoupling capacitance while reducing the required layout area, thereby suppressing parasitic effects during high-stage accumulation. A noise sampling compensation circuit is further employed to reduce accumulated circuit noise and improve the signal-to-noise ratio (SNR). The proposed accumulator is designed and verified using a 55 nm standard CMOS process. Post-layout simulation results indicate that the proposed design achieves a 20.945 dB SNR improvement under 128-stage accumulation, with the effective accumulation stage count approaching the ideal value. The total layout area is 4.711 mm × 88.43 mm. The proposed design demonstrates a potential approach for implementing compact, low-noise, and high-stage analog accumulators for TDI-CMOS image sensors.