UCIe Standard Package Rev 3.0 Ver 1.0 — Project presentation

Project presentation. **UCIe 3.0 PHY Layer Project Description** This project focuses on implementing the **PHY (Physical Layer)** of the **UCIe (Universal Chiplet Interconnect Express) 3.0** standard using **SystemVerilog**. To understand the idea, think of two separate chips that need to communicate with each other. The PHY layer is responsible for transferring data between them as electrical signals, ensuring the communication is fast, reliable, and synchronized. Our project implements the digital components of the PHY layer using a modular SystemVerilog design. Each module performs a specific function, such as transmitting and receiving data, handling synchronization, and supporting reliable communication between chiplets. The design is verified through simulation and testbenches using **QuestaSim** to ensure it behaves correctly under different scenarios then upload design on FPGA using VIVADO. The project provides hands-on experience with digital hardware design, RTL development, simulation, verification, and industry-standard chip-to-chip communication protocols. It also helps build a strong foundation in modern chiplet-based system design, which is becoming increasingly important in advanced semiconductor technologies.