Hierarchical Sorting Methodology Framework for Reducing Possibilities in High-Density Digital Systems

This work presents a two-layer hierarchical sorting framework designed to reduce the combinatorial explosion in high‑density digital systems. The method separates canonical entropy‑based partitioning from objective‑driven hierarchical merging, providing containment guarantees, a positional non‑overlap condition, and an information‑theoretic budget that links merge loss to mutual information. The framework clarifies the limits of deterministic aggregation, establishes when non‑overlap is possible, and formulates topology selection as an optimization problem. It also provides diagnostic tools for table refinement and correlation analysis between node outputs.

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-07-27
DOI
https://doi.org/10.5281/zenodo.21629824
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
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article

Hierarchical Sorting Methodology Framework for Reducing Possibilities in High-Density Digital Systems

Mohammed Almodiny
Zenodo (CERN European Organization for Nuclear Research)
VLSI and FPGA Design Techniques
article

Hierarchical Sorting Methodology Framework for Reducing Possibilities in High-Density Digital Systems

Mohammed Almodiny
article en

Abstract

This work presents a two-layer hierarchical sorting framework designed to reduce the combinatorial explosion in high‑density digital systems. The method separates canonical entropy‑based partitioning from objective‑driven hierarchical merging, providing containment guarantees, a positional non‑overlap condition, and an information‑theoretic budget that links merge loss to mutual information. The framework clarifies the limits of deterministic aggregation, establishes when non‑overlap is possible, and formulates topology selection as an optimization problem. It also provides diagnostic tools for table refinement and correlation analysis between node outputs.

Zenodo (CERN European Organization for Nuclear Research)
Openalex Percentile: Top 16%
VLSI and FPGA Design Techniques
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