Design and Functional Verification of a Car Parking Management System Using Verilog

Efficient parking management has become an important requirement for handling the growing number of vehicles in residential, commercial, and institutional environments. This work presents the development and simulation of a digital car parking control system using Verilog Hardware Description Language (HDL). The proposed design focuses on implementing a modular controller capable of monitoring vehicle entry and exit, maintaining an accurate occupancy count, and regulating access based on parking availability. The system is organized into independent functional modules, including vehicle detection logic, parking occupancy management, gate control, and parking status indication, enabling simplified design verification and future scalability. Access to the parking area is automatically permitted only when vacant spaces are available, whereas additional vehicles are restricted once the predefined parking capacity is reached. A comprehensive verification environment is created using Verilog testbenches to evaluate the controller under multiple operating conditions, including normal vehicle entry, vehicle exit, continuous traffic flow, parking-full operation, simultaneous sensor events, and system reset. Functional simulations performed in ModelSim validate the correctness of the control logic by analyzing occupancy count, gate control signals, parking status indicators, and state transitions under different test scenarios. The simulation results demonstrate stable and reliable controller operation with accurate parking occupancy management and deterministic FSM behavior. The proposed architecture provides a scalable digital framework that can be extended in future to support intelligent parking features such as multi-level parking control, vehicle authentication, automatic slot allocation, and smart parking guidance while maintaining a hardware-independent simulation environment.