Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

Explore the article titled Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology from IJIRT Volume 13, Issue 2. This study evaluates the effectiveness of teaching programs on waste management knowledge among women.

Authors

Publication Details

Journal
International Journal of Innovative Research in Technology
Published
2026-07-24
DOI
https://doi.org/10.64643/ijirtv13i2-207126-459
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
0.00
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article

Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

Suroju Sai Santhosh Kumar, Udutha Saritha
International Journal of Innovative Research in Technology
Low-power high-performance VLSI design
article

Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology

Suroju Sai Santhosh Kumar, Udutha Saritha
article en

Abstract

Explore the article titled Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology from IJIRT Volume 13, Issue 2. This study evaluates the effectiveness of teaching programs on waste management knowledge among women.

International Journal of Innovative Research in TechnologyVol. 13(2)
Openalex Percentile: Top 15%
Low-power high-performance VLSI design
DOIOpen Access PDFOpenAlex
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Low-Power Noise-Tolerant Domino Logic Design Using 7-nm FinFET Technology — Suroju Sai Santhosh Kumar, Udutha Saritha · International Journal of Innovative Research in Technology (2026) | TGRS Research Map | TGRS