TOSCA: Towards Semi-Centralized Scheduling in Dataflow Architectures via Hardware-Software Co-Design

Dataflow architectures are regarded as promising hardware accelerators in multiple domains due to their efficiency and flexibility. Contemporary applications impose demands on the dynamic scheduling capability of dataflow architectures. Nevertheless, existing approaches face challenges in achieving efficient dynamic scheduling for dataflow architectures: centralized scheduling incurs heavy control overhead due to the limited local agility, whereas decentralized scheduling suffers from constrained planning visibility due to the lack of global awareness. In this paper, we propose TOSCA, a semi-centralized scheduling method for dataflow architectures through hardware-software co-design. Firstly, we introduce a semi-centralized dynamic scheduling execution model, featuring on-demand triggering, global sensing, global-aware planning, and low-latency remapping. Secondly, we present a dataflow microarchitecture designed to support this execution model, synergizing global awareness with local agility through close collaboration of a global-monitoring controller and semi-proactive local PEs. Finally, we propose an adaptive load balancing scheme to efficiently select appropriate PEs as scheduling targets, leveraging the hardware flexibility to enhance parallelism while reducing cost. Experimental results show that in a wide range of representative applications, TOSCA achieves up to 1.52 × performance improvement and 1.40 × energy efficiency improvement over state-of-the-art dataflow architectures.

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Journal
ACM Transactions on Architecture and Code Optimization
Published
2026-07-24
DOI
https://doi.org/10.1145/3833878
Primary Topic
Embedded Systems Design Techniques
Type
article
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article

TOSCA: Towards Semi-Centralized Scheduling in Dataflow Architectures via Hardware-Software Co-Design

Dongrui Fan, Xiaochun Ye, Zhihua Fan, Wenming Li et al.
ACM Transactions on Architecture and Code Optimization
Embedded Systems Design Techniques
article

TOSCA: Towards Semi-Centralized Scheduling in Dataflow Architectures via Hardware-Software Co-Design

Dongrui Fan, Xiaochun Ye, Zhihua Fan, Wenming Li, Shantian Qin
article en

Abstract

Dataflow architectures are regarded as promising hardware accelerators in multiple domains due to their efficiency and flexibility. Contemporary applications impose demands on the dynamic scheduling capability of dataflow architectures. Nevertheless, existing approaches face challenges in achieving efficient dynamic scheduling for dataflow architectures: centralized scheduling incurs heavy control overhead due to the limited local agility, whereas decentralized scheduling suffers from constrained planning visibility due to the lack of global awareness. In this paper, we propose TOSCA, a semi-centralized scheduling method for dataflow architectures through hardware-software co-design. Firstly, we introduce a semi-centralized dynamic scheduling execution model, featuring on-demand triggering, global sensing, global-aware planning, and low-latency remapping. Secondly, we present a dataflow microarchitecture designed to support this execution model, synergizing global awareness with local agility through close collaboration of a global-monitoring controller and semi-proactive local PEs. Finally, we propose an adaptive load balancing scheme to efficiently select appropriate PEs as scheduling targets, leveraging the hardware flexibility to enhance parallelism while reducing cost. Experimental results show that in a wide range of representative applications, TOSCA achieves up to 1.52 × performance improvement and 1.40 × energy efficiency improvement over state-of-the-art dataflow architectures.

ACM Transactions on Architecture and Code Optimization
Institute of Computing Technology (CN), University of Chinese Academy of Sciences (CN)
Affordable and clean energy
Openalex Percentile: Top 4%
Embedded Systems Design Techniques
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TOSCA: Towards Semi-Centralized Scheduling in Dataflow Architectures via Hardware-Software Co-Design — Dongrui Fan, Xiaochun Ye, et al. · ACM Transactions on Architecture and Code Optimization (2026) | TGRS Research Map | TGRS