A PLC-Aware Benchmark and Evaluation Framework for Edge PCB Defect Detection Under Unified Training Protocols

PCB detector comparisons are often distorted by changed train/validation splits, input scales, training budgets, and hardware assumptions, which is unacceptable for PLC-coupled inspection. This paper establishes a PLC-aware benchmark for edge PCB defect detection by fixing the archived DeepPCB 1350/150 split, re-training principal external baselines under a common 896 px, 300-epoch protocol, and evaluating deployment through the delay model tau = t(s) + c * Delta t. Under aligned recognition, re-trained YOLO11n attains the best mean mAP50-95 of 0.8511, followed by Ezekias-style YOLO11n at 0.8495 and LPCB-YOLO at 0.7745. Within the native internal sim_rpi5 profile, Ours-LW records 0.8199 mean mAP50-95 with 40.11 ms latency, 24.93 FPS, 248.68 mJ proxy energy, and tau = 47.61 ms at c=1. Under the stricter all-route sim_rpi5-remapped comparison, Ezekias-style YOLO11n yields the strongest proxy deployment tuple at 45.48 ms, 21.99 FPS, 281.95 mJ, and tau = 52.98 ms, with YOLO11n close behind at 46.50 ms and 288.31 mJ. The benchmark therefore separates recognition leadership, native deployment judgment, and common-scale deployment ranking instead of collapsing them into one winner. YOLO11 hybrid attribution further shows that migrated P2/BiFPN/CA variants remain within 0.0060 mAP50-95 of the YOLO11n control, indicating that the current accuracy ceiling is driven mainly by backbone and retraining route rather than by replaying the older lightweight stack.