A Flexible FPGA-based Butterfly Engine for Accelerating Signal Processing and Machine Learning

Field-programmable gate arrays (FPGAs) have emerged as efficient accelerators for both neural network (NN) inference and digital signal processing (DSP) tasks, particularly on resource-constrained edge devices. While previous NN accelerators based on butterfly operations demonstrate significant acceleration for inference, they are inadequately suited for long sequences and lack support for bit-reversed access patterns, limiting their applicability to variable-length DSP workloads. Based on prior butterfly accelerators, this paper presents flexible butterfly engine (FlexBE), together with a co-designed NN architecture, Butterfly-based Signal Processing Net (BSPNet). The proposed system jointly supports signal pre-processing and butterfly linear (BL)-based NN inference under stringent resource constraints. FlexBE incorporates novel adaptive data switching networks, dynamic access control mechanisms, and an efficient bit-reversal module, enabling runtime reconfiguration of sequence lengths and degrees of parallelism. Implemented on an AMD ZCU104 FPGA running at \(300\) MHz, FlexBE computes four \(32\) k-point fast Fourier transforms (FFTs) in approximately \(15,360\) clock cycles. On challenging automatic modulation classification (AMC) datasets, BSPNet achieves accuracy comparable to GPU baselines. For single-batch inference, BSPNet with FlexBE is \(2.2\sim 3.1\times\) faster than prior butterfly-based accelerators; on the ZCU104, the end-to-end latency achieves speedups of up to \(4.92\times\) and \(2.89\times\) compared to an Intel Core i9 CPU and an NVIDIA RTX 3090 GPU, respectively.