Topology‐Aware Task Mapping Strategies for S‐NUCA Based Many‐Core Architectures

ABSTRACT Background Task scheduling in many‐core systems with static non‐uniform cache access (S‐NUCA) is complicated by spatial variability in cache latency and thermal hotspots. Prior research has considered cache asymmetry, inter‐thread distance, and locality, but these factors are often treated separately and predominantly within runtime‐based frameworks rather than being integrated into a unified compile‐time strategy. Objective To develop compile‐time topology‐aware thread mapping strategies that jointly address spatial cache locality and thermal constraints without incurring runtime migration overhead. Methods We propose three compile‐time thread mapping strategies, namely Golden‐Angle Spiral Mapping (GASM), Max Distance Anti‐Cluster Mapping (MDAC), and Latency‐Aware Minimal Mapping (LAMM). These approaches leverage geometric dispersion and Average Manhattan Distance (AMD) between cores to enhance spatial placement. Each mapping targets a distinct scenario, with LAMM designed for low‐thread compute‐bound workloads, MDAC for high‐thread thermally constrained cases, and GASM for irregular memory‐intensive workloads. These methods statically address thermal and latency constraints without runtime migration overhead, enabling low‐complexity mappings with predictable performance and thermal behavior. Results Across 8, 12, 16, and 64 thread configurations, the proposed topology‐aware mappings achieve up to 26% performance improvement and 16% energy reduction over the static baseline. Even when compared with the dynamic baseline, which benefits from runtime adaptation, they continue to deliver up to 20% higher performance and 9% lower energy consumption. Under workload‐specific thread configurations, performance gains reach 22% and energy savings 18%, with each mapping showing the benefit for its target workload behavior. Overall, these results validate the effectiveness of a complementary multi‐strategy approach for thermally constrained S‐NUCA many‐core systems.

Authors

Institutions

Publication Details

Journal
Software Practice and Experience
Published
2026-07-16
DOI
https://doi.org/10.1002/spe.70092
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Topology‐Aware Task Mapping Strategies for S‐NUCA Based Many‐Core Architectures

Anshu S. Anand, Jagpreet Singh, Anupam Jain, Venkatesan Subramanian
Software Practice and Experience
Parallel Computing and Optimization Techniques
article

Topology‐Aware Task Mapping Strategies for S‐NUCA Based Many‐Core Architectures

Anshu S. Anand, Jagpreet Singh, Anupam Jain, Venkatesan Subramanian
article en

Abstract

ABSTRACT Background Task scheduling in many‐core systems with static non‐uniform cache access (S‐NUCA) is complicated by spatial variability in cache latency and thermal hotspots. Prior research has considered cache asymmetry, inter‐thread distance, and locality, but these factors are often treated separately and predominantly within runtime‐based frameworks rather than being integrated into a unified compile‐time strategy. Objective To develop compile‐time topology‐aware thread mapping strategies that jointly address spatial cache locality and thermal constraints without incurring runtime migration overhead. Methods We propose three compile‐time thread mapping strategies, namely Golden‐Angle Spiral Mapping (GASM), Max Distance Anti‐Cluster Mapping (MDAC), and Latency‐Aware Minimal Mapping (LAMM). These approaches leverage geometric dispersion and Average Manhattan Distance (AMD) between cores to enhance spatial placement. Each mapping targets a distinct scenario, with LAMM designed for low‐thread compute‐bound workloads, MDAC for high‐thread thermally constrained cases, and GASM for irregular memory‐intensive workloads. These methods statically address thermal and latency constraints without runtime migration overhead, enabling low‐complexity mappings with predictable performance and thermal behavior. Results Across 8, 12, 16, and 64 thread configurations, the proposed topology‐aware mappings achieve up to 26% performance improvement and 16% energy reduction over the static baseline. Even when compared with the dynamic baseline, which benefits from runtime adaptation, they continue to deliver up to 20% higher performance and 9% lower energy consumption. Under workload‐specific thread configurations, performance gains reach 22% and energy savings 18%, with each mapping showing the benefit for its target workload behavior. Overall, these results validate the effectiveness of a complementary multi‐strategy approach for thermally constrained S‐NUCA many‐core systems.

Software Practice and Experience
Indian Institute of Technology Ropar (IN), Indian Institute of Information Technology Allahabad (IN)
Affordable and clean energy
Openalex Percentile: Top 4%
Parallel Computing and Optimization Techniques
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.