Compact Single-Transistor Ternary Content-Addressable Memory Based on Parallel-Channel WSe ₂ Reconfigurable Transistors

As data-centric applications such as AI and network processing grow rapidly, conventional computing systems suffer from performance bottlenecks due to the separation of memory and logic. Ternary content-addressable memory (TCAM) offers a promising memory-centric approach by enabling parallel search operations with three logic states—‘0’, ‘1’, and ‘don’t care’ (‘X’)—for enhanced functionality. However, conventional static random access memory (SRAM)-based TCAMs require at least 16 transistors per cell, limiting density and incurring significant power overhead. Here, we present a compact single-transistor TCAM cell based on parallel-channel reconfigurable field-effect transistors (PC RFETs) fabricated using large-area monolayer WSe 2 . The parallel-channel configuration enables stable ambipolar transport in large-area WSe 2, where selective charge-transfer doping with sub-stoichiometric metal oxides converts the homogeneous p-type WSe 2 channel into parallel n-type and p-type channels. A tri-layer Al 2 O 3 /HfO 2 /Al 2 O 3 gate stack enables nonvolatile modulation of p-type, n-type, and ambipolar conduction states via gate pulse programming. The PC RFETs demonstrates symmetric conduction ( I on.n / I on.p ≈ 1.02), high on/off ratios (∼10 5 ), and reliable match/mismatch behavior. This RFETs-based a single transistor (1T) TCAM cell is further validated through SPICE simulations. An 1 × 8 array simulation confirms scalability and circuit-level feasibility with a latency of ∼5 ns. This work offers a promising pathway toward high-density and fast operation with compact TCAM for future data-centric computing.