A 40.68‐MHz Active Rectifier Using PLL and PWM Control of DC‐DC Converter for ON/OFF Delay Compensation

ABSTRACT This paper presents a high‐efficiency active rectifier design for implantable medical devices (IMDs), where size reduction and power efficiency are critical requirements. Operating at 40.68 MHz allows significant miniaturization of passive components but also introduces substantial challenges in compensating ON/OFF delays during the rectification process. These delays can cause inaccurate switching instances, leading to increased conduction loss and degraded system performance. To address this issue, this work proposes a ramp‐based phase‐locked loop (RPLL) architecture that merges the timing controllability of pulse‐width modulation (PWM) techniques with the phase‐tracking capability of a phase‐locked loop. The proposed RPLL ensures accurate switching‐phase alignment, compensates delay variations, and stabilizes the rectifier operation. As a result, the rectifier achieves improved power conversion efficiency (PCE) and voltage conversion ratio (VCR), enabling reliable operation under the stringent power constraints of IMDs. The circuit is implemented in a standard 0.18‐μm CMOS process, ensuring manufacturability and low power consumption. Cadence simulation results demonstrate a peak PCE of 90.3% and a maximum VCR of 98.0%, verifying the effectiveness of the proposed architecture in high‐frequency wireless power transfer applications.