Mitigation of the Row-Hammer Effect in Sub-20 nm Dynamic Random-Access Memory (DRAM) Using Low-k Dielectrics

As dynamic random-access memory (DRAM) continues to scale down and achieve higher integration density, the cell layout has transitioned to 6F2, resulting in narrower spacing between adjacent word lines (WLs). Consequently, cell-to-cell disturbance has become more severe. In particular, the row-hammer effect (RHE) has emerged as a critical reliability issue that must be mitigated to ensure stable operation in next-generation DRAM devices. In this study, a novel DRAM cell structure is proposed, in which a low-k dielectric material is embedded beneath the storage node (SN) to mitigate the electric field. This structural modification effectively suppresses the RHE compared to the conventional partial-isolation type buried channel array transistor (Pi-BCAT). The feasibility and performance of the proposed structure were verified through 2D Sentaurus technology computer-aided design (TCAD) simulations. The device embedding the low-k dielectric beneath the SN exhibits a mitigation of approximately 20.45% in D0 failure and about 12.12% in D1 failure. This improvement is attributed to the reduced electric field in the region underneath the SN, which suppresses stored charge leakage. These results confirm that the proposed structure not only enhances DRAM reliability in advanced process nodes but also provides an effective design guideline for highly integrated and low-power memory devices.