Verification of training and compensation under variations: simulation and measurement on oxide semiconductor analog in-memory computing chips

Abstract Among various Analog in-Memory Computing (AiMC) implementations, those employing oxide semiconductors are promising due to their high energy efficiency. However, analog circuits are susceptible to variation and noise. Various techniques have been proposed to improve the accuracy on AiMC chips, and their effectiveness has been validated through simulations and evaluations. Nevertheless, no studies have verified the effects of variation and noise using actual AiMC chips fabricated using oxide semiconductors. This study demonstrates that there is an optimal combination of noise intensity during training and inference that improves accuracy using actual AiMC chips. Furthermore, measurements of multiple chips reveal a positive correlation between the chip’s inherent noise intensity and the optimal noise intensity during training. We also examined the differences between variation-aware training and Dropout techniques, which enhance noise robustness, and provided insights into achieving higher accuracy. The findings of this study should significantly contribute to the practical application of AiMC.