A Novel High-Frequency Simulation Methodology for IBIS Models Utilizing Verilog-AMS Dynamic Parameter Compensation

Conventional I/O Buffer Information Specification (IBIS) models often suffer from reduced fidelity in high-speed signaling because their static table-lookup mechanism cannot accurately reproduce complex transient I/O-buffer dynamics. To address this limitation, this study proposes a Verilog-AMS-based dynamic parameter compensation method. First, the conventional IBIS model is reformulated into a three-layer architecture comprising a data interface layer, an intermediate variable computation layer, and a port response synthesis layer. Then, based on Kirchhoff’s current law (KCL), the monotonic dependence of the output voltage on the pull-up and pull-down driving factors, kpu and kpd, is analytically derived to provide a directional criterion for parameter correction. Building on this criterion, a pulse-width-driven compensation algorithm is developed by constructing a pulse-width-indexed dual-factor empirical adjustment matrix and detecting the pulse width of the input bitstream in real time during transient simulation. The detected pulse width is then used to dynamically update kpu and kpd, enabling the IBIS response to converge toward the transistor-level SPICE reference waveform. Three representative device models were evaluated at 666 Mbps and 1.302 Gbps using pseudo-random binary sequence excitation, and the model fidelity was quantified using the normalized mean square error (NMSE). The proposed method reduced the NMSE from −6.73 to −1.03 dB before compensation to −54.79 to −44.19 dB after compensation, demonstrating a substantial improvement in high-frequency IBIS modeling fidelity and confirming the robustness and adaptability of the pulse-width-aware dynamic compensation strategy under random high-speed excitation.