Hardware-Enforced MAVLink Protocol Interposition: Stateful Header Inspection and Physics-Based Interdiction for UAS Cyber Defense

Unmanned aerial systems (UAS) built on the MAVLink protocol implicitly trust their command links: a flight controller largely executes what well-formed packets instruct. CVE-2026-1579 (CVSS 9.8), the subject of CISA advisory ICSA-26-090-02, demonstrated that this protocol-level trust is exploitable. Software patches mitigate specific instances but cannot remove the underlying trust-boundary violation, because the patch resides in the same trust domain as the target. This work presents the design and simulation-based verification of a hardware interposer that enforces MAVLink integrity below the operating system: an FPGA placed physically between the companion computer and the flight controller, performing stateful header inspection (system-ID allowlisting and sequence-continuity analysis) and, on violation, physics-based interdiction — galvanic severance of actuation signals within a sub-15 ms window chosen to corrupt malicious command execution without inducing kinetic stall. A fail-safe architecture ensures the security layer cannot itself cause mission loss. Verification comprises 22 unit-test checks (0 failures), a five-scenario full-system integration simulation (5/5), and live-traffic co-simulation against MAVLink UDP streams in which unauthorized-system-ID, sequence-jump, and flood attacks are each interdicted while legitimate traffic passes. All results are simulation-based; silicon bring-up is future work.