Task-Aware Design Boundaries for Approximate CMOS Image-Sensor Analog Front-Ends

Low-power CMOS image sensors increasingly rely on approximate analog front-end designs, including reduced ADC precision, relaxed voltage swing, and noise-tolerant readout circuits, to reduce energy consumption in always-on edge vision systems. However, the acceptable degradation boundary of such analog front-ends remains unclear when sensor outputs are consumed by downstream spatial perception workloads rather than conventional image-quality metrics. This paper presents a task-aware system-level evaluation framework for approximate CMOS image-sensor analog front-ends. We parameterize key circuit-level non-idealities, including ADC bit-depth reduction, temporal read noise, gain and offset variation, fixed-pattern noise, and dynamic-range clipping, and we evaluate how these impairments propagate through semantic, geometric, mapping, and spatial decision workloads. Across 10,500 end-to-end evaluations and 1996 geometric mapping trials, we identify a strong non-linear error cascade: semantic free-space extraction remains tolerant to aggressive quantization, whereas monocular depth and visual odometry impose much stricter analog front-end requirements. The results show that read noise and offset errors are the dominant failure sources for geometric perception, while controlled voltage swing clipping at 0.8 V can reduce front-end energy without degrading, and in some cases slightly improving, downstream reliability by suppressing high-intensity outliers. The analysis provides quantitative design boundaries for low-power CMOS image-sensor front-ends, including task-specific ADC precision, read-noise tolerance, voltage swing, PGA bypass, and offset calibration requirements.