Industrial wafer edge segmentation for alignment: a dual-resolution deep learning approach with synthetic pretraining and unsupervised geometry regularization

Accurate wafer alignment is crucial for successful three-dimensional integrated circuit fabrication. This task becomes particularly challenging when wafer-edge visibility is degraded by contaminants such as particles and adhesive residues, as well as variable illumination. We present a deep learning-based segmentation pipeline that detects wafer-edge geometries from high-resolution (2448 × 2048) images with pixel-level precision under such adverse conditions. Central to our approach is a dual-resolution U 2 -Net architecture that first localizes wafer edges from a low-resolution (306 × 256) image and then crops corresponding high-resolution regions for fine segmentation. This strategy enables efficient processing of large images with substantially reduced computational cost while maintaining alignment accuracy. In addition, we employ extensive training on synthetic wafer images generated via a custom simulator with systematic domain randomization, significantly reducing the need for costly real-world labeling. A novel unsupervised generative adversarial network (GAN)–based refinement stage further enhances segmentation quality by enforcing geometric plausibility through geometry-aware synthetic samples. Comprehensive evaluation shows that our method consistently outperforms baseline methods and conventional GAN variants, achieving mean intersection-over-union scores above 0.96 on real-world samples even when fine-tuned with only one labeled wafer image, defined as one annotated 2448 × 2048 image containing both carrier and device wafer regions. These results demonstrate strong robustness to occlusion and contamination, making the approach well suited for industrial wafer alignment applications.