Multirate Quasi-Cycle-by-Cycle Control of High-Switching-Frequency Three-Phase Current Source Rectifier

High-switching-frequency three-phase current source rectifiers can reduce passive-component size, but their short switching periods impose stringent real-time computational requirements on cycle-by-cycle digital control. This paper proposes a multirate quasi-cycle-by-cycle control scheme that separates computationally intensive control calculations from high-frequency control-input updates. A 10 kHz slow-rate interrupt service routine calculates a sequence of control inputs using the average model and second-order Lagrange interpolation, while a 100 kHz fast-rate interrupt service routine applies these inputs in successive switching cycles. Experimental validation is conducted on a three-phase current source rectifier operating at a switching frequency of 100 kHz and an output power of 409.5 W. With a multirate factor of N=10, the proposed scheme increases the effective control-input update rate from 10 kHz to 100 kHz. Compared with the conventional 10 kHz non-cycle-by-cycle control scheme, the proposed scheme reduces the input current total harmonic distortion from 14.50% to 4.02%, corresponding to a relative reduction of 72.28%. It also achieves a lower total harmonic distortion than the conventional 50-kHz control scheme, which produces a value of 6.06%. Accounting for both interrupt levels, the 20.59 μs slow-rate ISR and ten 3.30 μs fast-rate ISR executions require a total of 53.59 μs of processor time during each 100 μs slow-rate interval. This corresponds to an overall processor utilization of 53.59% and an overall computational redundancy of 46.41%, compared with only 8.85% redundancy for the conventional 50 kHz implementation. The maximum measured error of the Lagrange-reconstructed phase voltage is 0.2 V. These results demonstrate that the proposed scheme improves input-current quality while preserving sufficient computational margin for cycle-by-cycle control-input updating at a switching frequency of 100 kHz.

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Publication Details

Journal
Electronics
Published
2026-09-13
DOI
https://doi.org/10.3390/electronics15184144
Primary Topic
Multilevel Inverters and Converters
Type
article
Field-Weighted Citation Impact
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article

Multirate Quasi-Cycle-by-Cycle Control of High-Switching-Frequency Three-Phase Current Source Rectifier

Li Ding, Jianxiao Zou, Siping Feng, Zhiheng Yu et al.
Electronics
Multilevel Inverters and Converters
article

Multirate Quasi-Cycle-by-Cycle Control of High-Switching-Frequency Three-Phase Current Source Rectifier

Li Ding, Jianxiao Zou, Siping Feng, Zhiheng Yu, Dehong Zhou
article en

Abstract

High-switching-frequency three-phase current source rectifiers can reduce passive-component size, but their short switching periods impose stringent real-time computational requirements on cycle-by-cycle digital control. This paper proposes a multirate quasi-cycle-by-cycle control scheme that separates computationally intensive control calculations from high-frequency control-input updates. A 10 kHz slow-rate interrupt service routine calculates a sequence of control inputs using the average model and second-order Lagrange interpolation, while a 100 kHz fast-rate interrupt service routine applies these inputs in successive switching cycles. Experimental validation is conducted on a three-phase current source rectifier operating at a switching frequency of 100 kHz and an output power of 409.5 W. With a multirate factor of N=10, the proposed scheme increases the effective control-input update rate from 10 kHz to 100 kHz. Compared with the conventional 10 kHz non-cycle-by-cycle control scheme, the proposed scheme reduces the input current total harmonic distortion from 14.50% to 4.02%, corresponding to a relative reduction of 72.28%. It also achieves a lower total harmonic distortion than the conventional 50-kHz control scheme, which produces a value of 6.06%. Accounting for both interrupt levels, the 20.59 μs slow-rate ISR and ten 3.30 μs fast-rate ISR executions require a total of 53.59 μs of processor time during each 100 μs slow-rate interval. This corresponds to an overall processor utilization of 53.59% and an overall computational redundancy of 46.41%, compared with only 8.85% redundancy for the conventional 50 kHz implementation. The maximum measured error of the Lagrange-reconstructed phase voltage is 0.2 V. These results demonstrate that the proposed scheme improves input-current quality while preserving sufficient computational margin for cycle-by-cycle control-input updating at a switching frequency of 100 kHz.

ElectronicsVol. 15(18)
University of Electronic Science and Technology of China (CN), Shenzhen Institutes of Advanced Technology (CN)
Affordable and clean energy
Openalex Percentile: Top 51%
Multilevel Inverters and Converters
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