Novel Method For Power Consumption-Based Temperature Sensing In Soc Device.

Abstract A novel in-situ method to indirectly sense changing thermal properties of the TIM (thermal interface material) without using any onboard temperature sensors is demonstrated. The technique can detect the average junction temperature at specific computational elements (CPU, GPU) by the temperature dependent power consumption of these elements that have a periodically applied software stressor. The technique was demonstrated on a commercial system on chip (SOC) development kit. The temperature response for frequency modulated heating depends on thermal conductivity, density, and specific heat of layers making up the test package. By selecting the modulation frequency, the thermal penetration depth can be varied to probe individual layers in the build-up of the electronic package. The total power consumption is used to sense a spatially localized computational element's temperature (e.g. specific core) by way of temperature-dependent leakage current in transistors. Simulations using different thermal conductivities for the TIM show the sensitivity of this technique to TIM layer degradation. This technique's temperature measurements are validated against the chip's onboard temperature with good agreement (within 1K for ~25sqmm section in ~100sqmm SOC). Measurements by this technique make averaged measurements and can complement onboard temperature sensors, often located at periphery of the sensed unit. We found this SOC increases energy consumption with junction temperature by ~0.5% per K over large temperature rise and ~4% per K at around 333 K (60 °C), having implications for computational energy efficiency versus chip temperature considering advanced nodes have larger leakage current.