Design of LNA for GPR Application Using TSMC 130 nm CMOS Technology

This paper presents the design, simulation, and performance evaluation of a Low Noise Amplifier (LNA) for Ground Penetrating Radar (GPR) applications using TSMC 130 nm CMOS technology[1]. The proposed LNA is designed to operate in the GHz frequency range while achieving high gain, low noise figure, proper impedance matching, and reliable stability[10]. Traditional CMOS LNA architectures face challenges due to bulky on-chip inductors, limited quality factors, and area constraints[7]. This work explores a multi-stage cascaded common-source topology with inductive input matching to enhance RF performance. Key parameters such as gain (S21), transient behavior, stability, and signal integrity are analyzed. Simulation results demonstrate a peak gain of 17.71 dB with effective signal amplification and low distortion, making the design suitable for GPR and other RF receiver front-end systems. The study also examines technology scaling effects and discusses future trends in compact, high-performance LNA architectures[16].

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-06-26
DOI
https://doi.org/10.5281/zenodo.20922977
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Design of LNA for GPR Application Using TSMC 130 nm CMOS Technology

Kiran Bailey, Ramya Sheshadri, Purvi Ashwath, Purvi Chandrashekar
Zenodo (CERN European Organization for Nuclear Research)
Radio Frequency Integrated Circuit Design
article

Design of LNA for GPR Application Using TSMC 130 nm CMOS Technology

Kiran Bailey, Ramya Sheshadri, Purvi Ashwath, Purvi Chandrashekar
article en

Abstract

This paper presents the design, simulation, and performance evaluation of a Low Noise Amplifier (LNA) for Ground Penetrating Radar (GPR) applications using TSMC 130 nm CMOS technology[1]. The proposed LNA is designed to operate in the GHz frequency range while achieving high gain, low noise figure, proper impedance matching, and reliable stability[10]. Traditional CMOS LNA architectures face challenges due to bulky on-chip inductors, limited quality factors, and area constraints[7]. This work explores a multi-stage cascaded common-source topology with inductive input matching to enhance RF performance. Key parameters such as gain (S21), transient behavior, stability, and signal integrity are analyzed. Simulation results demonstrate a peak gain of 17.71 dB with effective signal amplification and low distortion, making the design suitable for GPR and other RF receiver front-end systems. The study also examines technology scaling effects and discusses future trends in compact, high-performance LNA architectures[16].

Zenodo (CERN European Organization for Nuclear Research)
Affordable and clean energy
Openalex Percentile: Top 10%
Radio Frequency Integrated Circuit Design
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Design of LNA for GPR Application Using TSMC 130 nm CMOS Technology — Kiran Bailey, Ramya Sheshadri, et al. · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS