Low-Power Design Implementation of AES-128-CCM Coprocessor for Secure Chip

This paper presents a low-power hardware implementation of an AES-CCM coprocessor for secure chips in embedded systems. The proposed design performs key expansion only once and stores the round keys in an on-chip RAM to avoid redundant computations. Meanwhile, the S-box module is shared between the key expansion and encryption to reduce hardware overhead. A dual-mode architecture supporting parallel (two-core) and serial (single-core) operations is implemented to adapt to high-throughput and low-power scenarios. The design supports AES-128, with a 1.25 Kb RAM used to store the 10 round keys. Experimental results using TSMC 40 nm technology show that the parallel mode achieves a 5.4% power reduction at the cost of 12.8% area overhead compared with the reference design. The energy efficiency reaches 2.11 pJ/bit in the parallel mode and 2.17 pJ/bit in the serial mode.