BridgedRing: A Cost-Effective Hardware-Software Co-Design to Overcome the UPI Bottleneck in GPU Servers
Distributed training on standard dual-socket GPU servers suffers from the “UPI Wall” — a bottleneck stemming from the interplay between the low physical bandwidth of the Ultra Path Interconnect (UPI) and the severe bidirectional contention induced by NCCL’s ring-based collectives. Software-only optimizations cannot overcome this hardware constraint. We present BridgedRing , a hardware-software co-design that bypasses the UPI Wall using an off-the-shelf NVLink Bridge costing approximately $200 — less than 0.5% of the total cost of a typical 8-GPU server. Our topology-aware algorithm redirects all cross-NUMA traffic through this high-bandwidth bypass while preserving intra-NUMA communication over PCIe. Evaluated on 8 × A6000 servers against NCCL and hierarchical algorithms: BridgedRing achieves up to 1.97 × higher collective bandwidth and delivers 1.31 × end-to-end throughput for GPT-13B training in Megatron-LM (TP=8, SP=8), 1.36 × for GPT-6.7B, and 1.40 × for Qwen3-1.7B in PyTorch DDP . Crucially, these gains require no framework modifications , offering immediate, cost-effective acceleration for the vast installed base of standard GPU servers.
Authors
- Yunming Ye (ORCID: https://orcid.org/0000-0002-1807-8581)
- Jianghong Ma (ORCID: https://orcid.org/0000-0002-0524-3584)
- Yakun Zhang (ORCID: https://orcid.org/0009-0009-2377-3114)
- Yihao Zhao (ORCID: https://orcid.org/0000-0002-7160-2485)
- Wanfeng Huang (ORCID: https://orcid.org/0009-0002-6560-0368)
Institutions
- Shenzhen Institute of Information Technology (CN)
- Peking University (CN)
- Nanjing University (CN)
Publication Details
- Journal
- ACM Transactions on Architecture and Code Optimization
- Published
- 2026-06-24
- DOI
- https://doi.org/10.1145/3822179
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00