Code Conversion of High-Resolution Vernier Time-to-Digital Converters

As the requirements in fields such as automobile, high-frequency signal generation, and medical applications, the resolution of time-to-digital converters (TDCs) has been pushed to the picosecond and sub-picosecond levels. In this study, a Vernier TDC was investigated with a time resolution less than the signal transition in the circuit. As generally happens in TDCs or Analog-to-Digital Converters (ADCs), bubble errors are found to degrade the resolution of their output codes. The bubble errors are usually attributed to non-idealities and mismatches in the circuits. Since the input time difference in high-resolution TDCs is much smaller than the signal transition time with the existence of bubble errors, it is an issue to determine the corresponding thermometer code from the output bit string of interleaved 0 s and 1 s. In our exploration, a Xilinx FPGA was employed to implement a Vernier Delay Line (VDL) for the TDC. In this timing-sensitive design, the timing difference between the two paths mainly comes from the interconnects rather than the Look-Up Table (LUT) devices. Timing constraints and regular placement were also imposed in addition to the simple Register Transfer Level (RTL) codes. Since the nature of uncertainty, a statistical model was proposed to analyze the output bit patterns. Three methods were employed to determine the output thermometer code. The first would count the total number of 1 s in the output. The second is to detect the position of the last 1. And the third is to detect the first 0 in the output bit string. The obtained results showed that these three methods were almost equivalent in the statistical outputs. The time resolution of our FPGA-based VDL can be around 5 ps in our measurement. According to our model, the transition time in the FPGA circuit was estimated as 100 ps. This result is reasonable for a chip made of 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. For the study of the linearity of our VDL, its differential nonlinearity (DNL) was less than ±2 LSB. The code-density-like analysis also shows the nonlinearity of this VDL. It was also found that the methods detecting the last 1 and the first 0 were sensitive to bit failures. In summary, for this study, it is confirmed that the three conversion methods are equivalent, and we found that detecting the last 1 or the first 0 was sensitive to bit defects or mismatches.