p-GaN Layer Etch Engineering for Defect Reduction in 200 mm Enhanced-Mode AlGaN/GaN HEMT Processing
Gate definition is a major challenge in p-GaN gate AlGaN/GaN HEMT structures because of the high selectivity and low plasma damage required during the etching process. In this work, self-terminated etching, developed to limit surface damage and loss of the underlying AlGaN layer, is investigated. A comparison of two over-etch chemistries (Cl2/O2/N2 and BCl3/SF6) revealed that the oxygen-based process yields superior results in terms of AlGaN surface morphology, producing a smoother surface and a more conformal p-GaN profile, while the fluorine-based process exhibited more anisotropic behavior, leading to p-GaN residues and surface pitting. To address across-wafer non-uniformity, a temperature gradient strategy using the tunable electrostatic chuck was developed. The optimized process was evaluated through automatic defect control and device robustness under drain bias-stress. A total reduction in defectivity and reliable HEMT devices across the wafer under high drain-source bias were achieved. These results demonstrate the effectiveness of the proposed solution, offering significant improvements in process efficiency and manufacturability.
Authors
- Sébastien Avertin
- A. Constant (ORCID: https://orcid.org/0000-0002-0957-7450)
- Mohammed Zeghouane (ORCID: https://orcid.org/0000-0002-2268-5106)
- Giovanni Giorgino (ORCID: https://orcid.org/0000-0002-9462-0328)
- Pauline Gaillard
- Ferdinando Iucolano
- Hyon-Ju Chauveau
- Julien Drieu La Rochelle
Institutions
- STMicroelectronics (France) (FR)
- STMicroelectronics (Italy) (IT)
Publication Details
- Journal
- Electronics
- Published
- 2026-06-17
- DOI
- https://doi.org/10.3390/electronics15122690
- Primary Topic
- GaN-based semiconductor devices and materials
- Type
- article
- Field-Weighted Citation Impact
- 0.00