An Enhanced Latency-Bounded GPU-Resident Pipeline for Real-Time Market Stream Visualization

High-Frequency Trading (HFT) dashboards require rapid reception, aggregation, and visualization of order book and trade update streams that may arrive at multi-million message rates. Conventional CPU-based and CPU-GPU hybrid visualization pipelines can suffer from significant delays during periods of burst due to CPU-mediated rendering, synchronization, kernel launch overhead, and copies on the host. This paper presents a visualization pipeline that is entirely resident on the graphics processor with zero-copy access to NIC accessible pinned buffers, persistent CUDA processing, fused stage execution of the parse-aggregate pipeline, and persistent CUDA OpenGL buffer interoperation. The goal is not to reach production status but rather to see whether host-to-host data movement can be decreased and whether the stages of GPU processing can be consolidated to improve latency, throughput and frame cadence in controlled HFT-style workloads. The evaluated workstation achieved a mean ingest-to-pixel latency of 6.3 ms using the proposed design compared to 29.4 ms for the current design, with sustained throughput of 10.2 million messages per second, which is 20 times greater than the current design, and a steady-state range of 185 to 192 frames per second with a burst floor of 178 frames per second for the proposed design. The improvement observed can be attributed to both the zero-copy ingestion and fused persistent kernel execution. Based on the obtained results, the proposed method of use of this technique in the implementation of real-time financial visualization under the proposed conditions is possible. More general testing is still required on other NICs, other generations of GPUs and PCIe configurations, workload traces, and actual exchange feeds.