Design of 8‐Bit Dadda Multiplier and Divider Using Logic Level Pruning Approximate Arithmetic Circuits

ABSTRACT Arithmetic circuits are the basic building blocks of frequently used computational systems. As the functions used in the computational system increase, the design constraint effects are proportional to the requirement. Approximate computing is a technique with the advantage of controlling design constraints by trading off accuracy. Approximation has major challenges in image processing, speech processing, and machine learning. So, an image‐processing blending application, noise removal, or changing the transparency of images are designed using arithmetic circuits like adders and subtractors, respectively. Here, an 8‐bit Dadda multiplier and a restoring divider are designed using approximate compressors and subtractors, respectively. The approximate full adders and full subtractors are implemented using tabular manipulation methods and logic‐level pruning. The full adders are replaced either in the MSB or the LSB positions for better accuracy and error analysis. Image processing blending application, and background removal are performed using MATLAB, and design constraints are evaluated using Synopsys DC Compiler. The results show the logic‐level pruning compressors, multipliers, and restoring dividers get a 40%–70% gain in PDP.