FPGA-Based Reconfigurable SoCs for Safety-Critical AI Inference: A Systematic Literature Review

Field-programmable gate array (FPGA)-based reconfigurable system-on-chip (SoC) platforms are increasingly deployed in safety-critical domains such as autonomous driving and industrial automation, yet the existing literature lacks a systematic assessment of how these designs address functional safety requirements. This paper presents a systematic review of 36 peer-reviewed studies (core period 2010–2024, with historical context from 1998) on FPGA-based reconfigurable parallel processing SoCs, analyzed through three frameworks: a convergence–divergence analysis (CDA) that provides a structured exploratory lens for identifying research trajectory trends and informing hypothesis generation; a safety-critical gap analysis benchmarked against a three-layer standard framework comprising ISO 26262 (functional safety), ISO 21448/SOTIF (safety of the intended functionality), and ISO/PAS 8800 (AI safety properties); and a four-dimensional design space taxonomy spanning reconfigurability granularity, parallelism exploitation, design automation level, and safety criticality. The analysis reveals that 33 of the 36 surveyed studies (92%) ignore safety certification entirely. While recent work has begun establishing worst-case execution time (WCET) bounds for FPGA SoC platforms, none of the surveyed FPGA-based AI accelerator studies provide WCET bounds, although recent analytical models for multi-DPU architectures demonstrate the feasibility of such analysis. FPGA CNN accelerators achieve energy efficiencies of up to 60 GOPS/W, and dynamic partial reconfiguration (DPR) yields 2–5× throughput improvements, yet these gains remain unsupported by the formal verification or uncertainty quantification mandated for safety certification. The CDA framework reveals strong convergence between DPR, network-on-chip (NoC), and high-level synthesis research threads (scores 0.72–0.91), indicating maturation toward integrated design flows. We identify conformal prediction as a distribution-free hardware-compatible framework for uncertainty quantification on resource-constrained FPGAs, motivated by requirements from ISO 21448 (triggering event identification) and ISO/PAS 8800 (runtime confidence monitoring), and propose a prioritized research agenda to bridge the gap between FPGA performance optimization and safety-certified deployment in transportation systems.