Voltage compensation of manufacturing errors applied to artificial band gaps in nanoscale transistor

A nanoscale MOS transistor possessing an embedded SiO 2 -Si-SiO 2 quantum well serving as source-drain channel is presented. To examine the influence of significant variables on discrete quantum energy levels, band gap, and optoelectronic characteristics of the electrical potential distribution through the channel, an advanced numerical model has been designed. Since the channel thickness – the key parameter for the light emission wavelength – is not always uniform between devices in the same fabrication batch, we propose using activation voltages to compensate for manufacturing errors in the Si-SiO 2 interfaces of the quantum well. The expected benefits include the control of light emission through electrical voltages (V GS , V DS ) and the channel thickness (t Si ), the mitigation of parasitic currents through the insulation buried oxide layer, and a completely VLSI-compatible design for swift industry integration based on Si and SiO 2 . Through calculating the eigenvalues’ distribution along the channel length (L), we argue that electrical compensation of Si layer process mismatch can modulate the inter-sub-band transitions (ISBT) when applying adequate activation voltages. This is of particular importance for long (L) and large (W) channel transistors, as it is necessary to ensure a significant quantity of hot electrons for triggering the ISBT efficiently.