Physics-Inspired Deep Learning and Bayesian Optimization for Surrogate Modeling of Nanosheet and Forksheet Transistors

The continued scaling of semiconductor devices at advanced technology nodes introduces significant challenges in maintaining performance, reliability, and design efficiency. This work presents a data-driven framework for the modeling and optimization of nanosheet (NS) and forksheet (FS) transistors using deep learning and Bayesian optimization. An extensive dataset is generated through LTSpice-based circuit simulations, enabling efficient exploration of the design space while incorporating key device parameters, including channel length, channel width, supply voltage, temperature, and threshold voltage, together with variability and noise effects. A deep neural network (DNN) is developed as a surrogate model to learn the nonlinear relationship between input parameters and transistor switching behavior, achieving strong predictive performance with a coefficient of determination (R2≈0.91), mean absolute error (MAE ≈0.024), and root mean square error (RMSE ≈0.031) on unseen test data. To improve physical consistency, a bounded-output formulation is introduced to guarantee physically admissible voltage predictions, while device-level benchmarking is performed to assess agreement with expected transistor characteristics. The results demonstrate accurate modeling of transient behavior across the sampled operating conditions. Comparative analysis shows that NS devices achieve faster switching and lower propagation delay, whereas FS devices exhibit improved stability under certain conditions. Bayesian optimization is employed to efficiently explore the design space and identify high-performing transistor configurations without exhaustive simulation-based searches. The proposed framework provides a scalable and computationally efficient methodology for surrogate modeling, design-space exploration, and early-stage assessment of advanced transistor architectures.