Chaotic clock generator for CPA-resistant image encryption based on a novel wide parameter range chaotic map

Abstract This work is an attempt to address some issues related to practical hardware realization of power attack-resistant chaos-based encryption schemes. First, we introduce a new two-dimensional chaotic map based on a modified logistic-tent map. The proposed map has a very wide range of sustained chaotic and hyper-chaotic behavior over its large key parameters space. The presented map is practically realized using a digital field programmable gate array. Experimental validation of the map’s enhanced chaotic behavior is provided. Then the map is employed to efficiently generate chaotic clock signals appropriate for reliable image encryption applications. A proposed image encryption scheme which is driven by the generated chaotic clock signals is designed. The immunity against the powerful correlation power analysis attack is achieved in the proposed image encryption scheme even in the case when some secret key parameters of the encryption process are leaked. The present study paves the way to further explore how to build efficient chaos-based encryption schemes immune to other types of well-known effective attacks.