Lock-Step ISS-vs-DUT Verification with Automated Test-Case Minimisation

A method for verifying the correctness of an RTL device-under-test (DUT) CPU core by executing an identical instruction stream on both a validated golden software ISS and the DUT via RTL simulation, comparing full architectural state after each retired instruction, and automatically minimising any diverging test case to its smallest reproducer using the ddmin algorithm. The ISS is implemented in Rust with zero runtime heap allocations. The DUT is compiled to a cycle-accurate C++ model via Verilator (open-source). This is a defensive publication placing these techniques in the public domain as prior art