A 15 dBm CMOS Class-J power amplifier achieving 47% PAE and 20 dBm OIP3 for Bluetooth low energy application

Purpose This study aims to present the design and implementation of a Class-J CMOS power amplifier (PA) targeting Bluetooth Low Energy (BLE) applications, addressing the critical requirements of efficiency, linearity and compact integration for low-power wireless communication. Design/methodology/approach Fabricated in 180 nm CMOS process, the proposed PA integrates an analog pre-distortion (APD) stage to enhance linearity by introducing opposing third-order nonlinearities to those of the main amplifier. Class-J operation is achieved through harmonic tuning, and an active load in the APD eliminates bulky passive RF chokes, reducing chip area. The PA is optimized for 2.45 GHz operation and characterized through on-chip measurements to validate performance. Findings The measured results demonstrate a forward gain (S21) of 20.5 dB, with input/output return losses (S11/S22) of −20.6 dB and −19.9 dB, indicating good impedance matching. The PA achieves a saturated output power of 15 dBm and a peak power-added efficiency of 47%. Linearity is confirmed with a third-order output intercept point of 19.9 dBm at an output power of 6.1 dBm, along with suppressed third-order intermodulation distortion (IMD3). The amplifier maintains unconditional stability across 1 GHz to 5 GHz with a stability factor (Kf) greater than 1. Originality/value The proposed PA demonstrates that a compact and linear Class-J architecture with APD can be effectively implemented in standard CMOS technology, making it well-suited for BLE transmitters in IoT and wearable devices.