Accelerating Active Learning for Image Classification Through FPGA-Based Implementation

Image sensors produce high-dimensional visual data for classification algorithms. Deep Neural Networks (DNNs) achieve high accuracy but require large labeled datasets and computational and energy resources, limiting their use in embedded systems. Active Learning (ALrn) can reduce labeling effort by selecting samples based on informativeness scores, but it remains computationally expensive, especially for high-dimensional images. This work presents a hardware-accelerated approach for the instance selection stage based on a query strategy in uncertainty-based ALrn for image classification using a novel in-line top-k selection algorithm that avoids conventional sorting and reduces memory and computational requirements. The algorithm is implemented on an Xilinx ZYNQ-7000 System on Chip (SoC) using a Field Programmable Gate Array (FPGA)-based accelerator operating at 110 MHz, interfacing with an embedded Advanced RISC Machine (ARM) processor for data acquisition and communication via the Python Productivity for Zynq (PYNQ) framework. Experiments on diverse multiclass datasets demonstrate correctness within an ALrn setting, showing negligible performance deviation in the learning curves compared to software baselines. The accelerator achieves speedup of 231.7× and 22.9× over software baseline and optimized software implementation of the proposed algorithm, respectively, in query-strategy computation while consuming only 0.473 W, substantially lower than conventional Central Processing Unit (CPU)- and Graphics Processing Unit (GPU)-based platforms. These results demonstrate the efficiency and extensibility of the proposed accelerator across alternative ALrn designs and hardware platforms, where the computational cost of instance selection scales with the size of the unlabeled pool.