Verbinden van transistormetrologie en kwantumdotprestaties voor het testen van siliciumspinqubits op waferschaal

The rapid development of quantum technologies requires scalable qubit platforms capable of combining high coherence with industrial manufacturability. Among the competing quantum technologies, silicon spin qubits stand out due to their intrinsic compatibility with CMOS fabrication, long spin coherence times, and potential for high-density integration. Their practical deployment, however, still faces crucial limitations, one of the most significant being testing throughput. The extremely low-temperature environment, in the millikelvin range, required for qubit characterization makes device testing slow, expensive, and fundamentally incompatible with the throughput needs of industry. The ability to identify promising functional qubit devices before cryogenic measurements, ideally already at room temperature, has therefore become a key enabling step for future large-scale quantum processors. This PhD project develops, validates, and demonstrates a full design, fabrication, characterization, and simulation framework addressing this challenge. It explores room-temperature transistor metrics as reliable screening parameters for quantum dot quality, while simultaneously proposing a new single-electron transistor, or SET, architecture optimized toward room-temperature electrostatic confinement to enable such screening. The PhD work begins by situating silicon spin qubits within the wider landscape of quantum technologies and highlighting the scaling bottlenecks posed by their variability, interface disorder, and low-temperature testing. The work first introduces the device structures at the core of the project: SETs whose geometry mirrors the building blocks of larger quantum dot arrays. Because SETs permit both room-temperature transistor characterization and quantum dot formation at millikelvin temperatures, they provide a relatively simple platform and an ideal model system to investigate whether electrical signatures at room temperature can be used to predict quantum dot behavior at cryogenic temperatures. The fabrication flow, gate-stack materials, maskset organization, and integration constraints are detailed to connect the device performance to process-induced effects such as interface roughness, silicon/silicon dioxide interface disorder, and dopant-induced electrostatic disorder. The core of the PhD work demonstrates that a small set of transistor-level metrics, namely the threshold voltage, the subthreshold swing, the maximum transconductance, and the off-state current, encode meaningful information about the electrostatic environment that ultimately governs quantum dot formation. A wafer-scale statistical analysis of 1,488 SET gates between 225 K and 300 K is performed to quantify the variations and correlations of device behavior across temperature. These results are combined with extensive millikelvin quantum dot characterization, including Coulomb diamonds and barrier map analysis. The work shows that, in the SET devices used, the correlation between transistor metrics and quantum dot performance is strong and robust from deep-cryogenic temperatures up to 77 K. This correlation progressively degrades as the temperature approaches 295 K, due to the onset of uncontrolled conductive paths in the substrate. The work identifies the root cause of this breakdown: insufficient electrostatic confinement at high carrier densities, which allows carrier transport far from the intended quantum dot region. This insight highlights the need to design new devices that maintain confinement at room temperature, without relying on physical isolation that could otherwise degrade qubit performance. To validate these conclusions and guide the design and layout of future device generations, this PhD project develops a calibrated three-dimensional TCAD transport simulation framework capable of reproducing the measured drain-current versus gate-voltage characteristics from 295 K down to 77 K. The model incorporates interface-charge effects, series-resistance contributions, realistic gate geometry, and temperature-dependent mobility. After detailed calibration, the simulations generate the current-density distribution inside the SET at different temperatures and expose the failure modes responsible for the loss of confinement at room temperature in the original SET design. Based on this foundation, the project then proposes and evaluates a new SET design with all gates located on a single layer and with an extended confinement gate surrounding the active region. Simulations predict that this optimized geometry suppresses parasitic current paths and improves the on-current to off-current ratio by up to four orders of magnitude at room temperature, restoring the electrostatic behavior required for meaningful high-temperature screening of SETs before committing them to cryogenic cool-down. In addition to device characterization, the PhD work also develops a design methodology that integrates room-temperature-aware constraints directly into the early stages of qubit-device layout. This methodology is demonstrated on the new optimized SET layout and generalizes to more complex multi-dot structures. By ensuring channel confinement at all temperatures, this new device layout will enable room-temperature test flows in future fabrication cycles, considerably reducing the number of devices that must undergo long cool-downs to millikelvin temperatures and thereby accelerating the path toward wafer-scale qubit manufacturing and testing. Overall, this PhD work provides a systematic correlation study linking wafer-scale room-temperature measurements to millikelvin quantum dot quality. It identifies electrostatic confinement as the key enabler for room-temperature screening of qubit structures, delivers a validated TCAD framework to model cryogenic transport, and proposes a new scalable, fabrication-compatible SET design and layout that enables meaningful room-temperature characterization without compromising qubit performance. Together, these advances form a unified body of work offering a concrete tool for accelerating the testing and further development of silicon spin-qubit technologies.