Native oxide-engineered 3D-graphene/silicon photodetectors for imaging sensors and photonic logic applications

Silicon-based optoelectronic devices typically use hydrofluoric etching to remove native silicon oxide (SiO2) from silicon (Si) surfaces, thereby eliminating the interfacial insulating layer and reducing the interface barrier. However, this process increases fabrication complexity and introduces a large density of dangling bonds and interface defects. In this study, the native SiO2 layer is intentionally retained to serve as an additional barrier and tunneling layer. A three-dimensional (3D) graphene/SiO2/Si heterostructure is constructed that alleviates lattice and chemical mismatches between the 3D-graphene and Si. This design minimizes dark current and enhances tunneling transport of photogenerated carriers. The porous 3D-graphene creates nanoscale resonant cavities that improve light absorption through multiple scattering and localized optical field enhancement. The device exhibits long-term stable (4 months) and efficient photoresponse from 380 to 1550 nm, achieving 20 A/W responsivity and 6.9 × 1010 Jones detectivity at 1550 nm, with rapid response times of 180/191 μs. It enables optical signal encryption, photonic logic gate operations (AND/OR), and near-infrared imaging with a pixel array of 200 × 200. This work reveals the role of native oxide layers in Si heterostructure design and offers a strategy for enhancing broadband Si photodetectors.