Research on Imaging Test System and Multifunctional Image Algorithm Based on Cooled Infrared Focal Plane Detector Circuit

This paper proposes a cooled infrared focal plane circuit and detector imaging test system. The system features online acquisition, temperature monitoring, bias voltage programming, real-time imaging, and online testing capabilities, improving the testing and verification efficiency of infrared focal plane detector imaging systems. Temperature monitoring accuracy reaches ±0.02 K; bias voltage programming keeps bias noise below 100 nV/Hz1/2; and a 2 × 2 pixel image array is used for data transmission, enabling algorithmic computation on pixel data for convenient image processing. Furthermore, this paper proposes various image algorithms and overall algorithm structures based on a single-chip pixel-level ADC, the dynamic range is 141.8 dB, and the maximum input charge capacity is 4.46 Ge−. The overall structure of the multifunctional image algorithm for infrared focal plane detectors is summarized, including background subtraction, blind pixel compensation, non-uniformity correction, windowing, pixel merging, spatial filtering, histogram equalization, and time delay integration (TDI). Non-uniformity is improved by 98.3%, blind pixel rate is reduced by 92.3%, background subtraction performance is improved by 93%, and spatial filtering and TDI improve relative spatial noise by 63% and 89%, respectively. Pixel merging can increase the gray mean by 4.09 times, enabling arbitrary windowing and uniform histogram distribution. These highly practical research efforts will drive the further development of future larger-array cooled infrared focal plane array (IRFPA) detector imaging test technology and more intelligent infrared image algorithms.