Reconfigurable Logic‐in‐Memory Operations Enabled by Triple‐Gated Feedback Field‐Effect Transistors for Area‐Efficient Computing

In this study, we demonstrated reconfigurable combinational logic‐in‐memory (LIM) operations using a reconfigurable LIM (R‐LIM) cell composed of eight triple‐gated feedback field‐effect transistors (TG FBFETs). The proposed R‐LIM cell provides voltage‐based, stable, and highly symmetric outputs, resulting in strong noise immunity. Moreover, it enables multiple logic operations within the same circuit configuration and under identical input‐voltage conditions. In this study, program gates are employed as input terminals to enable combinational logic operations without requiring multiple R‐LIM cells to cascade. With the proposed approach, combinational logic functions such as a full adder, full subtractor, 2‐to‐1 multiplexer, and 4‐to‐2 encoder are implemented within a single R‐LIM cell configuration without cascading. Furthermore, the proposed R‐LIM cell exhibits logic‐retention capability under zero‐bias conditions and achieves more than an 80% reduction in the transistor count compared with other R‐LIM approaches. These results demonstrate that the R‐LIM cell is a strong candidate for next‐generation area‐efficient LIM computing systems.