Hardware Performance Characterization of a Closed-Form Complex-Domain Encoder: Compute, Memory, Energy, and Latency for Real-Time and Edge Deployment

This revised deposit contains the Paper 6 manuscript (PDF and DOCX) along with the supplementary reproducibility archive. The manuscript files were added in this revised version of the deposit; the supplementary ZIP file remains unchanged from the original deposit. Manuscript targets IEEE Transactions on Parallel and Distributed Systems (under preparation). Coverage. 10 pre-registered studies (Studies 79-82 from Phase XV; Study 90 from Phase XVIII; Study 92 from Phase XIX; Studies 95-97 from Phase XX of the spiral-domain encoder validation campaign). 30 hypotheses, 26 SUPPORTED (87%), 4 honest bounded negatives substantively interpreted. Substantive findings. NumPy CPU throughput plateau 47,500 subj/s; PyTorch MPS GPU plateau 220,000 subj/s; CPU/MPS crossover at K approximately 30; single-frame latency p99 = 12.13 microseconds, p99.9 = 34.13 microseconds (29x under 1 ms surgical RT budget); linear T-scaling slope -0.978 (vs theoretical -1.0); 0.07 mJ/subject on MPS GPU (4-400x more efficient than typical edge-ML inference); INT16 encoded-state and INT8 federated-coefficient compatibility for Cortex-M class embedded deployment. Contents. Manuscript (PDF and DOCX of the paper itself); supplementary reproducibility archive containing: README.md (submission-package map and reproduction instructions); preregistrations/ (frozen pre-registration .md documents with literal-threshold decision rules); reports/ (per-study .md verdict reports against frozen rules + phase summaries); runners/ (deterministic Python runners under PYTHONHASHSEED=0); raw_data/ (per-study CSV outputs and JSON verdict blocks); figures/ (manuscript figures at 300 DPI + figure-build script); code/ (encoder source code). Reproducibility. Full validation pipeline is reproducible end-to-end under PYTHONHASHSEED=0 on a standard Python 3.9+ installation with NumPy 2.0+ linked against the Apple Accelerate framework, plus PyTorch 2.8+ with MPS backend for the GPU portions. Reference machine: Apple Silicon arm64 (M-series), macOS 14. See README.md for per-study run commands. Methodological discipline. Every hypothesis was pre-registered with externally anchored decision rules frozen prior to runner execution. Zero post-hoc threshold adjustments were applied. Honest bounded negatives are interpreted substantively rather than discarded. Related companion archives. Paper 1 (10.5281/zenodo.20129137), Paper 2 (10.5281/zenodo.20138786), Paper 3 (10.5281/zenodo.20139171), and the corresponding Papers 4, 5, 7, 8 archives in this same Zenodo collection (Paper 8 at 10.5281/zenodo.20466035).

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-05-30
DOI
https://doi.org/10.5281/zenodo.20466994
Primary Topic
Embedded Systems Design Techniques
Type
preprint
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preprint

Hardware Performance Characterization of a Closed-Form Complex-Domain Encoder: Compute, Memory, Energy, and Latency for Real-Time and Edge Deployment

Randolph James Ferlic, Kimberly Kate Ferlic
Zenodo (CERN European Organization for Nuclear Research)
Embedded Systems Design Techniques
preprint

Hardware Performance Characterization of a Closed-Form Complex-Domain Encoder: Compute, Memory, Energy, and Latency for Real-Time and Edge Deployment

Randolph James Ferlic, Kimberly Kate Ferlic
preprint en

Abstract

This revised deposit contains the Paper 6 manuscript (PDF and DOCX) along with the supplementary reproducibility archive. The manuscript files were added in this revised version of the deposit; the supplementary ZIP file remains unchanged from the original deposit. Manuscript targets IEEE Transactions on Parallel and Distributed Systems (under preparation). Coverage. 10 pre-registered studies (Studies 79-82 from Phase XV; Study 90 from Phase XVIII; Study 92 from Phase XIX; Studies 95-97 from Phase XX of the spiral-domain encoder validation campaign). 30 hypotheses, 26 SUPPORTED (87%), 4 honest bounded negatives substantively interpreted. Substantive findings. NumPy CPU throughput plateau 47,500 subj/s; PyTorch MPS GPU plateau 220,000 subj/s; CPU/MPS crossover at K approximately 30; single-frame latency p99 = 12.13 microseconds, p99.9 = 34.13 microseconds (29x under 1 ms surgical RT budget); linear T-scaling slope -0.978 (vs theoretical -1.0); 0.07 mJ/subject on MPS GPU (4-400x more efficient than typical edge-ML inference); INT16 encoded-state and INT8 federated-coefficient compatibility for Cortex-M class embedded deployment. Contents. Manuscript (PDF and DOCX of the paper itself); supplementary reproducibility archive containing: README.md (submission-package map and reproduction instructions); preregistrations/ (frozen pre-registration .md documents with literal-threshold decision rules); reports/ (per-study .md verdict reports against frozen rules + phase summaries); runners/ (deterministic Python runners under PYTHONHASHSEED=0); raw_data/ (per-study CSV outputs and JSON verdict blocks); figures/ (manuscript figures at 300 DPI + figure-build script); code/ (encoder source code). Reproducibility. Full validation pipeline is reproducible end-to-end under PYTHONHASHSEED=0 on a standard Python 3.9+ installation with NumPy 2.0+ linked against the Apple Accelerate framework, plus PyTorch 2.8+ with MPS backend for the GPU portions. Reference machine: Apple Silicon arm64 (M-series), macOS 14. See README.md for per-study run commands. Methodological discipline. Every hypothesis was pre-registered with externally anchored decision rules frozen prior to runner execution. Zero post-hoc threshold adjustments were applied. Honest bounded negatives are interpreted substantively rather than discarded. Related companion archives. Paper 1 (10.5281/zenodo.20129137), Paper 2 (10.5281/zenodo.20138786), Paper 3 (10.5281/zenodo.20139171), and the corresponding Papers 4, 5, 7, 8 archives in this same Zenodo collection (Paper 8 at 10.5281/zenodo.20466035).

Zenodo (CERN European Organization for Nuclear Research)
EP Analytics (United States) (US)
Embedded Systems Design Techniques
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