Hardware masking with buffer chain

Abstract Side-channel attacks pose a major threat to cryptographic implementations, as they can exploit physical leakages to recover secret information. Masking is one of the most widely adopted countermeasures, aiming to protect sensitive intermediate values by randomization. However, when deployed in hardware, masking faces the challenges from the glitch leakage, which can easily undermine the security integrity of masking techniques and affect the foundational independent assumptions upon which they are based. To address the intricacies of hardware implementation, circuit separation using registers has emerged as a straightforward method. In this paper, we investigate low-latency hardware masking by exploring the use of buffers (rather than registers) to prevent glitch propagation. Rather than directly inserting buffers into the circuit path, our approach involves employing a chain of buffers to generate signals that serve as controls, thereby synchronizing blocks that require sequential computation. This significantly reduces the power consumption of the shielding circuit while also decreasing latency within the circuit.