Optimization of Plasma Etching Process for 25:1 High Aspect Ratio Through‐Silicon Vias

ABSTRACT The advancement of 3D integration technology has driven demand for micro‐scale, high aspect ratio (HAR) through‐silicon via (TSV) etching, establishing it as a critical semiconductor manufacturing technology. Current 3D stacking implementations typically utilize TSVs with aspect ratios of approximately 10:1. To enable higher‐density interconnects in next‐generation applications, achieving substantially higher AR TSVs is imperative. However, within the photoresist (PR) mask system, high aspect ratio TSV etching faces challenges of insufficient etch selectivity and PR mask collapse, both of which constrain further aspect ratio scaling. This study proposes an optimization strategy for key process parameters. Through parametric optimization of chamber pressure, source power, and bias power, we achieved significant enhancement in selectivity and completely eliminated PR mask collapse. Ultimately, an aspect ratio of 25:1 was successfully demonstrated on TSVs with a critical dimension (CD) of 3 μm.